Methods and apparatuses consistent with the exemplary embodiments relate to a memory device, and more particularly, to a memory device which may reduce the pre-charge time of a global bit line by arranging a pre-charge circuit between sub-arrays, a pre-charge controlling method thereof, and devices having the same.
Semiconductor memory devices are memory devices which may store and read data when necessary. Semiconductor memory devices are primarily divided into volatile memory devices and non-volatile memory devices.
Volatile memory devices include dynamic random access memory (DRAM) and static RAM (SRAM) and so on. Non-volatile memory devices include programmable read only memory (PROM), erasable PROM (EPROM), an electrically erasable PROM (EEPROM), flash memory, ferroelectric RAM (FRAM) using a ferroelectric capacitor, magnetic RAM (MRAM) using a Tunneling magneto-resistive (TMR) film, and phase change RAM (PRAM) using chalcogenide alloys. The PRAM has a relatively simple manufacturing process and may realize large memory capacity at a low price.